A quantitative analysis of processor-programmable logic interface

The addition of programmable logic to RISC machines has the potential of exploiting the inherent paral-lelism of hardware to speedup an application. In this paper , we study the eeect of adding a programmable accelerator to DLX, a RISC prototype. We build this model and parameterize the communication overhead between the processor and programmable unit and logic/routing delays inside the programmable unit. We use simulation to evaluate the performance of this model, parameterized by communication overhead and logic delays, by comparing it with the baseline DLX architecture on some sample problems. Our methodology is useful in studying the relative importance of the parameters and in projecting the performance of the system, if the programmable logic were to be implemented inside the processor.